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Hi,
Thanks for your reply.
Im looking for the methology of gate calculation / or do have any standard libaray for it?
Example with an HDL code as below with a Macros function ADD,
architecture ADDER of A_design is
begin
ASYNCHRONOUS_State0_SM : process (A,b,c)
begin
X <= "00";
X <= ADD...
Hi,
Im under an research on:
1) How to do the gate count from a set of HDL code / Macros?
2) What is the gate systhesis methology or design flow?
appreciate that can share with me the resources of the info.
thank your very much!
regards,'
yh
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