Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by sw0ws1

  1. S

    body terminal of NMOS in triple well technology

    Thanksssssssssssss 4 ur reply what i understand that the body of MO1 will be always connected to node vout1 and this will be valid in the two phases??right thanks in advance
  2. S

    body terminal of NMOS in triple well technology

    vout1=node A =3VDD mO1 and MO2 are the NMOS,VO1 is the node B (it takes the volts 3VDD-Vth and 5VDD-Vth) my question is about body terminal of MO1 i wish it be more clear now thanks 4 ur help
  3. S

    body terminal of NMOS in triple well technology

    Thanks for ur reply yes my circuit is a charge pump and i use the nMOS in last stage to have a voltage fluctuation......but i dont understand this statement "pre-charge node B with the body diode in phase II." could you please make it clear for me?? thanks in advance
  4. S

    body terminal of NMOS in triple well technology

    [B]hi all my question is about the connection of body terminal of NMOS ( i use triple well technology;in which the body terminal of NMOS can be connected to its source) the defination of source in circuit is the terminal that has the lowest voltage??? Am i correct?? the case in my circuit is as...
  5. S

    layout post simulation and the schematic simulation is different

    Hi all my question is the post layout simulation is different from schematic simulation(eff=62% in schematic and eff=52% in post layout)??i have no idea what to do?? how can i modify the layout to fit the schematic simulation?? thanks in advance
  6. S

    error in opening layout(locked file)

    Hi i just have a problem in opening the layout file (can't open it for edit but for read only) and i notice this warning message in terminal "warning file/root/cd.log file is already locked by some other process) So please, do anyone have any solution???:cry: thanks in advance
  7. S

    DRC error(vertice is drawn off-grid)

    Hi I have this DRC error (vertice is drawn off-grid) what does this error mean?i have no information about it except the previous statement can anyone help me??? thanks in advance
  8. S

    NMOS bulk connection - (2 wells: twell inside nwell)

    thanks for all of u the problem is solved i used M1_pdiff contact and add new twell and nwell to avoid the DRC errors.... thanks again
  9. S

    NMOS bulk connection - (2 wells: twell inside nwell)

    Re: NMOS bulk connection logically i think the doping of twell is p-type to form NMOS but i don't know this is true or not??
  10. S

    NMOS bulk connection - (2 wells: twell inside nwell)

    My problem is the bulk connection of nmos because my nmos is located in two wells, twell and nwell, the twell is located inside the nwell (as i upload here) ,my question is 1-i think the twell is the bulk of the nmos/is this true?? 2-how i connect the bulk of nmos(twell) to its source ( i...
  11. S

    should i use RF mos to avoid body effect?

    hi i use 0.18UM180FDKMFC-FDK in my design i have to avoid body effect so i need to connect the bulk terminal of NMOS to its source but the problem is the process is twin well so can i use RF mos in the kit?it has 4 terminals (s,D,G ,B) , when i see RF transistor layout it has a layer called DNW...
  12. S

    knowing of vt of nmos using virtuoso

    Thankssssssssssssssss for all of u, i will try this
  13. S

    knowing of vt of nmos using virtuoso

    Hi i use virtuoso in simulation, i just want to know the threshold of the nmos i used?? i followed the following steps -i performed dc analysis and save dc operation point -from menu -->i choose annotate -->dc operating point -i go to schematic and expect to find the vth of mos but i didnt find...
  14. S

    bulk of nmos in TSMC .25u tech

    thanks for your help i know that ,from transistor layout i can know if it is possible to connect its bult to source or not. if i find deep Nwell layer in the layout,so i can connect bulk to source but i don't know how i get this from Virtous could anyone please tell me how i see transistor...
  15. S

    bulk of nmos in TSMC .25u tech

    thanksssss for your reply how i know that i use a double or triple well process ???from technology ??or layout of used transistor??? thanks again
See more

Part and Inventory Search

Back
Top