Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi RCA,
I appreciate the response.
But doesnt dc_shell use the same wire load models, and loads the same libraries (fast, slow, tt libs for best, worst, tt cases) for the estimations?
Although, I would like to know more about how these estimations are more precisely done in topo mode?
I was...
I'm trying to learn more about the topo mode with Design Compiler.
And other than few additional commands that the topo mode has, I couldnt tell the difference.
Thanks for any clues on this.
S
Hey, were you able to solve the issue?? I'm facing the same problem...
I used -allow_undefined_module as suggested by the error message.
So, its not giving any errors now... but I don't see the FRAM being used in my top level module.
Thanks.
---------- Post added at 05:38 ----------...
Hello,
Im trying to plot Vt0 vs. Vgs keeping a Vds constant.
In the 'pick a visible trace' list, I can see all the currents and the circuit voltages - but not the device parameters.
Please find the circuit below - its a real simple circuit.
Any help is appreciated.
Thanks
ssti
no.... i use 8.1 and im having the same error.
I also get the same error (rather warning) after it imports a LEF file.
@busoni: The module for which you get the 'antenna' error - is is a hard macro by any chance?
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
