Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi,
One can use digital control on regulating the bias current by using parallel current sources.
Basic comparator to compare the input signal, compare with reference and turn on/off the biasing legs.
One can also add/remove the input differential pair, like one does to get rail to rail...
Hi,
From design point of view, if one wants to use LV device for HV supply operations.
On has to use cascading, or extended drain structures for reliability.
One should run GOX or SOA sims before putting such design onto production.
Supreet
Hi,
Some of the technology only support high Vt transistor and want to operate from 1.5V to 5V.
We have such in our company, which also has nhvnative transistor with almost 0 Vt.
Then we can use the topology 2 with top transistors as nhvnative and bottom mirroring transistor as HV nmos.
By...
Hi,
If you are able to plot AC gain Vs Freq plot (AC simulation using feedback)
Then the Gain at low freq is your DC gain.
Else you can run DC simulation also to know your DC gain.
Note:
Test bench for AC simulation with feedback
1. Use feedback resistance with AC component of 1e12 and...
The total area is not just W*L. If we are talking about the poly gate area, sometimes default value for poly extension is added in layout, which is not present in schematic. Also if we are talking about whole transistor area, then gate to contact spacing and LOD comes into play, which may not...
There are 2 parts to the total rise time delay namely, slew rate limited one which is totally decided by the output stage current, and bandwidth limited delay or ringing before settling, which is decided by gain of op-amp. In this case the slew limited delay is (8-4)/0.8=5us and the delay...
Hi,
The loop has a negative feedback which ensures that output node (drain of pmos) follows the input value. However this only the case if it is "biased" properly. When we apply small-signal or sine wave of small amplitude we do not disturb the quiescent point of the system, where the gain...
You can add a weak pull down. When the supply is floating, it will be pulled to low by this resistance. then you can use the same supply an ur signal. Usually when the supply is cut off, it decays to lower voltages automatically, because of various leakages. If u need to have a signal which...
latex circuit
Hi,
U can use Xfig. It is very easy and has more options. U can also export to .ps format directly from opus. Or use gimp to take snapshot directly and save as jpg file.
Enjoy
Hi,
We only want the DC portion of the output to go to negative terminal, so that the op-amp is properly biased. So we use C and L to send only dc portion in feedback. And then we can apply the ac voltge seperatly on inegative terminal, to see the gain on the output.
Supreet
Folded cascode are better as they provide high gain and also a high common mode voltage range. U can independently increase the 2nd stage current to decrease the slew rate dependent settling time and 1st stage gain to decrease bandwidth limited settling time.
As if the switched cap circuits are...
what is vih
Hi ,
Vih is basically a dc phenomenon, but due to hysterysis effects present in some circuits, it will differ from Vih(dc) depending on input signal transient behaviour. U can give a PWL waveform at input with relevant rise time (1us or 1ms) and see the cross over of input...
The transient response of an amplifier has two components:-
slew rate limited which is present approx till output reaches 70-80% of final settling value.
bandwidth limited, which will limit the remaining time fot it to settle and is depenedent on bandwidth.
When we play around with gain and...
Many times the models provided for subthreshold operation are not very accurate and hence we usually avoid putting trasistors in sub0threshold, except for current mirroring transistors.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
