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Recent content by supercst

  1. S

    Multiple bit error correction using reed-muller correction code

    help!!!! too much to learn, hdl, eda tools, and prototye board
  2. S

    Looking for info about clock latency in digital circuits

    clock latency In digital circuits, clock latency is clock delay, which may be clock delay from out of the chip. or clock delay inside the chip by clock buffer insertion.
  3. S

    Which FPGA is better: XILINX or ALTERA?

    Xilinx or @ltera xilinx is more controllable, altera is more easier for beginner
  4. S

    How to connect the FPGA to a PC without using a JTAG cable?

    help in fpga The usb is not a JTAG download cable?
  5. S

    [FPGA xilinx] UCF/NCF constraint files ?

    xilinx ise ucf file If you use GUI, the ncf with same name of the netlistfile and in the same directory will be automatically used by ISE
  6. S

    How to write data on the dual port RAM?

    Re: REALLI NEEED HELP!! please decribe clearly. what's your problem?
  7. S

    how to implmathmatical function in fpga such as cos,sin etc

    Re: how to implmathmatical function in fpga such as cos,sin use edatools coregen like xilinx or ip tools like altera
  8. S

    How can I add constraint for clk2 and data1 when I synthesis my block?

    Re: a synthesis problem create_generated_clock
  9. S

    Which country has best opportunities (work and Pay) in VLSI

    us salary for vlsi 9 years exp china mainland
  10. S

    what's difference between USB2.0 and USB1.1 ?

    usb1.1 difference usb2.0 the phy for 2.0 is very complex than 1.1, 1.1 phy is only two buffers. and the protocol is very different.
  11. S

    Can function be used in Verilog RTL?

    Re: function used in RTL maybe not suggested. only task can only be used in testbench. sometimes function will be convenient for some circuits. almost all the systhesis tools support functions.
  12. S

    Synthesis constraints

    synthesis constraints check snug doc or synopsys user manual for detail
  13. S

    recevei from USB flask disk

    go to usb.org for usb storage class spec. also you need to know the FAT file system and SCSI command
  14. S

    Why I can't get the correct counter?

    if you want a asynchronous reset/synchronous enable counter always ©(posedeg clk or posedge clr) begin if(clr) counter <= 0; else if(en) counter <= counter + 1'b1; end if you want synchronous reset/synchronous enable counter always ©(posedge...
  15. S

    2 questions concerning Synopsys PrimePower

    In my opinion, PP can't do power analysis in RTL phase.
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