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two options:
1. plan the power at top level before partition
2. plan the power for every partition and make the power stripes as a power pin. And connect those power pins at top level
If you only want to run gate level simulation by verilog-xl, it's not necessary to import netlist to icfb. You can run verilog-xl directly. For example,
verilog $verilog_netlist -v $verilog_library -y $verilog_library_path
$verilog_library can be found in which library installed.
Hi all,
Do you have ever met this case?
Timing result based on RSPF file is different from that based on SDF file.
The RSPF file was extracted from post-layout database by HyperExtract. And the SDF file was converted from that RSPF file by Pearl or PKS. The design can pass STA in PKS with RSPF...
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