Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi,
+
The question is specific to the at-speed testing for sure.
Simple answer is
1. If you can balance the clock skews, u can test the combo logic between the clock domains. (pulsing all the clocks during capture)
2. If not (why!!), u can not do nothing. Just get the top up coverage after...
Hello Friend,
Normally, u can compress the test patterns using Tetramax tool using different options like merge, auto_compression etc..
However, at ATE level, you can process these test vectors for further compressoin .
I'm not sure of ur requirement. However, if you are talking abount FDRs...
Hello Friend,
It looks you haven't followed the correct flow.
1. Synthesize (design compiler in ur case)
2. Insert test structure using test logic insertion tool (may be DFT Comlier in ur case)
3. Look for violations during post "dft_drc" (dft_drc after insert_dft).
4. Analyze and Fix the...
Hi...
At first,
"2. as process shrinking to under 65nm. at-speed test may needed. What make this happen? We can not keep a enough margin to STA? or STA can not model the chip accuratly? or OCV make the corner based STA in-sufficient? "
as tech node lowers, there is more bandwidth for...
hi jyothi,
if im correct, you have a design with registers that supports the data to load serial or parallel. And selection of serial or parallel data loading is done by a multiplexer.
Now the question1 is, how can we eliminate above multiplexer replacing with scan flops such that it supports...
sol1:
multiplex the functional pins for the purpose of scan
sol2:
scan compression technique.
however, test time directly relation with the length of scan chain.
sunil budumuru
hi friends,
how abt the following combo ckt...?
very optimistic solution....
its a thought but need some development and discussion on this.
Sunil Budumuru
SETUP HOLD STEP BY STEP
try to reduce the combo delay at the prelayout STA itself. to avoid such logic optimization during CTS stage, we do prelayout STA.
So it is always considered to have a timing clean netlist for PNR stage.
So it is always considered to have a timing clean netlist for PNR...
SETUP HOLD STEP BY STEP
there are different ways that we can follow to fix setup.
1) reduce freq
2) reduce comb delay
3) reduce clk-q delay
4) play with skew
(A)
if your design is not operating at the required frequency whats the use. it should be the last option. atleast one should not...
in broad sense realistic behavior of a chip is nothng but the manufatured chip that meets your design specifications and design requirements.
realistic behavior deals not only with the pre cts (what we are discussing here)
simply, ot indicates the exact requirement in terms of timing area...
a good estimation of time and area aspects of the design leads more clouser to the realistic behaviour of the chip.
So pre-cts stage is also equally important for a better estimation of the design and avoids last minute surprises.....
good luck
Sunil Budumuru
hello friend,
this ckt will not work due to 100ps hold violation.
tsk+th </= tcomb + tc2q
(-200) + 500 < 100+100
300 < 200
so there is 100ps hold violation. here skew is -ve.
play with skew or increase your combo delay (not suggestable most of the times)
i prefer a better skew balancing...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
