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After running AC simulation, use .probe vt(net) for group delay at net.
For ac simulation, vdb, vi, vm, vp, vr and vt symbols are used, which probes
DB decibel
I imaginary part
M magnitude
P phase
R real part
T group delay
Dear,
You misunderstood my question. Actually I have a flip flop of standard cell library. Now its setup time is fixed. Recently in one interview I was asked how can we reduce that setup time. And the answer was, if we connect the flip flops in cascade we can reduce the setup time with out...
Circuit design
try exor gate where one input is clock and another is feedback from output with some delay. use buffer or even number inverters.
Added after 49 seconds:
for delay, use buffers or even number of inverters
verilog code for fft
hi,
I believe, instead of searching book for DFT's and FFT's Implinetation with verilog, you should try to understand various algorithm for DFT and FFT. Xilinx and altera are providing ready made DFT and FFT verilog code.
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