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how are you so sure that the problem is in line 15 of my code? i have not even uploaded my code.
My code goes like this
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
use...
I am packaging my custom logic with axi lite and in customization window I get xpath unbalanced parantheses error. I have used generic in my code and in top module I have used generic map also. Still this error. What should I do to resolve this?
Hello ads-ee, i have to connect this AES IP core to AXI module and make an internal IP out of it with no I/O's going external of the FPGA. All the I/O's of the AES IP core have to be converted into internal nets. How am i supposed to do it? Do you have any example or document which explains this...
Hello All,
I am trying to synthesize AES encryption algorithm in vivado which was uploaded on open cores as shown in the link below
https://opencores.org/project,aes-128_pipelined_encryption
When I synthesize it, i get the following errors
Can someone tell me how to rectify these errors?
Thanks for the reply. I shall go through the document.. Is it like for Vivado IPs, I don't need to bother about the timing constraints at all. If I write HDL code of my own, then how am i suppose to calculate the set up and hold times? Is set up and hold time applicable only for the design which...
Hello All,
I want to write the timing constraints file in Vivado and I know that vivado constraints wizard will help me to do it. However I want to know if timing constraints have to be written for each and every logic design which we do in HDL. If yes then how do I calculate set up and hold...
I basically want to know the access cycles of DDR, block RAM and on chip memory over the AXI
- - - Updated - - -
where do i find the PS access latencies?
Hello All,
I am searching for data memory access cycles in arm cortex a9 which should include arbitration overhead by specific bus (AXI or LMB etc). I searched it in the arm cortex and microblaze manual. Please tell me where i can find it.
I am not very new to this type of work. The reason why i asked was to know when exactly I should use the PS DMA and when exactly the AXI DMA IP core. If I enable the PS DMA, I don't find any mechanism through which I can connect to Microblaze.
Hello All,
I plan to use DMA in Zynq PS and connect it with Microblaze. I need to transfer data to and from Zynq PS to microblaze using this DMA. I found in the configuration wizard that the Zynq PS has its DMA in the form of peripheral request interface and when I enable this it appears on the...
Hi,
Is it a good idea to create our own wrapper file according to which inputs I require. There is a possibility of letting vivado manage the wrapper file. However, I think it would be a good idea to create a second wrapper file on top of the 1st one according to which inputs and outputs which...
Thanks a lot DPaul. I assigned the ports which I didn't require as open in the top level wrapper file. When I did this and then ran synthesis, the vivado threw an error. I have attached a snapshot of the error. My command within the portmap of the top level wrapper file is as mentioned below...
Hello All,
I am using Zynq 7000 SOC in my design. I have enabled UART 0 and UART1 in the PS with extra modem signals. In addition to this, I need to create 2 more UARTs on the PL side for which I have chosen UART 16550 IP core. All 4 UARTS are 4 wired. ie they include TX, RX, RTS and CTS...
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