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yes, I am doing preCTS clock tree analysis. There is an option in the analysis window find -> min/max path, but I cannot access that( its disabled). Yep , I do find clock reports for fanout, cap etc.
By that sentence, I meant I get the report for timing giving values with no violation paths.In...
Yes..u are right. I am new to Physical Design but regarding the timing analysis i m doing the preCTS one. I have got reports (preCTS) and they display values.
The clock tree analysis doesn give me an option to find min/max path. CAn u suggest what changes/corrections I should make for the...
Hi all,
I am using the encounter for the first time. I have loaded the design, done the routing also the clock tree. Can view the timing analysis. But how do i make changes to timings like reduce slew rate , delay etc? Is there any graphical option where i can do something like simulation or do...
Actually I created only a header using the tech file(.tf) file I had got along with the package.
There is about 12 to 13 layers , via's etc. Do I need to create the definitions to each one of them manually?
Or is there any other I could do? Thanks a lot for help!
Hi all,
I got a new TSMC .13um kit from MOSIS. But I am having problems accessing them.
It has separate technology file(.tf) and the lef files. Because of this I am unable to import the design into the encounter. Its an ARM processor.
Has anyone done this before. Could you please guide me as in...
yes ...lef/tpd013n2_4lm.lef is the lef file, but it does not have a technical description(" header ") for the lef file. The first thread shows that.. hence i created one manually thats posted in my second thread. This header did remove the initial error and warnings but still the lef loading...
Thank you so much for the help. I did the changes, now I don get the warnings but
it still gives the metal1 error.
**ERROR: (ENCLF-53): The layer 'METAL1' is not found in the database.
A layer must be defined before it can be referenced.
Its defined the same way in the tech file too as...
Hi,
I am using ARM TSMC design kit of .13 um an loading the verilog and the LEF files directly from those. But I get an error below everytime i try import design.Coud anyone please help me solve it? Thanks in advance..
Loading Lef file ../Back_End/lef/tpd013n2_210a/4lm/lef/tpd013n2_4lm.lef...
Hi, I did find LEF files for the 25um technology. But now the problem is with the mtarpt fie. It fails to load saying the no failing paths or library missing. I tried making changes to the sdc file,
yet it says the same. Anyone please help!!!
Hello,
I am doing a project on designing a SoC using RTL to GDSII encounter v9.1.
I am new to this stuff, hence I am planning to start with an 8 bit microsystem.
Could you help me to start with? I was wondering if there is any possibility of
getting verilog and LEF files for the MCU so that i...
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