Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Sorry there, Im new to this forum as well.
Here is my code, I hope somebody can really help me with this.
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
USE STD.TEXTIO.ALL;
USE IEEE.std_logic_TEXTIO.ALL;
ENTITY std_logic_ram IS
PORT (address : IN std_logic_vector...
I have a RAM code here in VHDL where I have to convert to Verilog.
VHDL seems very complicated on its grammar and I am new to this field.
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
USE STD.TEXTIO.ALL;
USE IEEE.std_logic_TEXTIO.ALL;
ENTITY std_logic_ram IS...
Can anyone help me to solve this?
Design RAM using "module RAM (ramaddr, ramin, cs, rwbar, opr, ramout);"
with ramaddr, ramin, cs, rwbar, opr as input and ramout as output.
I am new to verilog design and I am wondering why clk isn't included in the port list.
Aren't ramaddr and ramin the same...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
