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Recent content by sujittikekar1

  1. S

    having drc violations in tmax

    tmax violation c8 Hello all, I am getting some C8 and C11 violations in drc reports in tmax. following is decription of violations C8- clock path affected by new capture on LS input 2 of DLAT C11- Clock connects to LS clock/data inputs 2/3 of DLAT How to get rid of these violation? also...
  2. S

    less fault coverage due to redundant faults

    Can anybody suggest the way to reduce these redudant faults?
  3. S

    less fault coverage due to redundant faults

    redundant faults following is my test coverage report from tetramax. (collapsed faul coverage report) #faults #detect #posdet #undet #redund testcov faultcov ------- ------- ------- ------- ----- -----...
  4. S

    DFT - are there any ways to improve fault coverage?

    Re: DFT fault coverage Thanks. I will try that option. But will it improve fault coverage?
  5. S

    DFT - are there any ways to improve fault coverage?

    Re: DFT fault coverage I used command run atpg -auto_compression because I have compression mode in my design. will -full_sequential command work for compressed patterns?
  6. S

    DFT - are there any ways to improve fault coverage?

    Re: DFT fault coverage I am using Tmax tool. I did not see set_scan_configuration command in Tmax? Do you talking about DC?
  7. S

    DFT - are there any ways to improve fault coverage?

    Re: DFT fault coverage Thanks for reply. I am using sequential atpg. How to use full scan? what r the settings we have to use for that? Do I have to fix bi-di pins in my design? or do they get fixed automatically( I am talking in regard with stuck-at fault model). Thanks in advance.
  8. S

    DFT - are there any ways to improve fault coverage?

    DFT fault coverage I have 95.30% fault coverage. I used test point insertion method to improve it but didnt help much (it increased by .2% only) I have around 13k AN faults in design. Most of these are due to constraints blockage,which I used for scan mode. Does anybody know other ways to...
  9. S

    need some artical on verification

    can anybody send some good links or book names or pdfs on verification components like monitor, checkers, scoreboards etc....
  10. S

    want help in System verilog.

    Hello all. i want to write a code for simple 3 bit asynchronous counter in verilog. and testbench in system verilog. Can anybody send the both Thanks in advance
  11. S

    Looking for info about using System Verilog for verification

    Hello to all. I want to start System verilog for verification. I am new to it. can you send me the links and books name related to this. Thanks in advane.
  12. S

    Why we dont consider the hold time of source flip-flop for calculating max. frequency

    can anybody tell why we dont consider the hold time of source flip flop while calculating max. frequency?
  13. S

    negative setup and hold

    what is negative setup and negative hold? please explain in detail.
  14. S

    predictive berkely transistor models

    back annotated delay what is meaning of back annotation? please describe in detail. Thanks in advance.:D
  15. S

    difference between SAIF and VCD file

    Can anybody tell the difference between SAIF file and VCD file? which one is used where?
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