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modelsim iteration
Hi Ajeetha,
I do not understadn what you are saying. What is SDF and how do I generate it or get it? I am new to FPGA/VHDL/Synthesis. This is my first project. Please help me. and delay_mode_unit where is this available? I did post-synthesis in ISE webback...
modelsim iteration limit
Hi,
My VHDL code works fine when I do a pre-synthesis simulation. It does synthesize also. But, when I try to simulate the post-synthesis code it says iteration limit reached. vsim 3601 error. nd delay truncated. I do not understand why this is happening. If there...
send data from pc to fpga
I am to do a tester chip in FPGA which is used to test other ICs so I need to transfer the test vectors and expected responses to the RAM in FPGA to be utilized for the DUT later. This is whr I need serial communication. BTW how do you transfer bits using Hyper...
Thanks for all your replies. I am to build a tester chip using FPGA to test some ICs..basically the RAM in FPGA stores the inputs(test vectors) and the expected responses. The test vectors are fed to the DUT and the output collected from DUT is sent to FPGA back to be compared with the expected...
I did not understand it. Clock source as in external clock source? Or I need to write some vhdl code to generate clock source? can you explain it a little more? I am new to all this so slow in understanding.
generate ic from fpga
Hi,
I need to generate clock from FPGA to drive another IC which is connected to the FPGA. Do I use a frequency divider or something to achieve ths where in I take the master clock from FPGA clock and generate the new clock? I am clueless about this. Help me with...
uart fpga computer
Sixdegrees,
You mean to say by using hyperterminal I don't have to write any C code for communication is it? And I have another problem. the input to the FPGA is going to bits as in I am designing a tester chip which takes in test vectors as inputs and...
open core fpga serial port
Hi,
I am doing a project using FPGA( a tester chip) and I am a graduate student. I am to transfer test vectors (1s and 0s) from a PC user interface to the FPGA RAM using serial port(computer's COM port). I leanrt how to configure the FPGA to send and receive data...
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