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Hi i have posted this before and had no luck, maybe there is someone who can help me , as i urgently need it.
The problem is, i am sending 16 bit data samples to the PC along a serial link. they are obviously being sent 8 bits at a time. I want to somehow store these samples being sent and then...
Hi,
I am not very familier with C. Where would i write this program and how would i get it runnin ?
You dont know of any programs out there that would do this for me ?
I have one running , but i cant save the data as HEX or binary .
Hi everyone,
I currently have a sierial link up and running and i am sending 8 bit words to the PC along this link.
What i want to do is capture this data and input it to MatLab. Does anyone know of any programs that will allow me to capute this data from the serial port in binary or HEX...
Hi everyone ,
I have implemented a serial link where i am sending data from an FPGA board to the PC. I have a program called RealTerm, which reads the input data, you can view this in binary and decimal which is what i want as i want to take this data and plot it in MatLab, the only problem is...
Hi Everyone,
just a quick question.
I have created a FIFO using CoreGen and in this part there are various clocks for read and write, i want to clock the write clock at ~ 75MHz, when you look in the vhdl file that is produced, it says in the "configuration specification" that the wr_clk = 100...
Re: Clock Problem...
Hi , thanks for the reply.
I have had an idea, since the board comes with a footprint to attach an clock source , can i not just take a wire from my clock out pin to the output of that footprint ? it then gets connected to the FPGA pin and can be my clock source ?
Stuart
Hi Everyone,
I have a small problem with regards clocking , am sure there is an easy soloution but want to know what you all think.
Right... i am using a XUP Virtex II Pro Evaluation board.
https://www.xilinx.com/univ/xupv2p.html
I am attaching an ADC board to this FPGA board, the ADc board...
Hi everyone ,
I am using a XUP Virtex II Pro Eval Board with ISE Foundation.
I want to clock something at double the source clock speed, i have been told that this can be done using a PLL?
Does anyone know how i go about this? can this part be generated using coregen ?
Stuart
I am currently using the XUP Virrtex II Pro eval board and have a clocking problem in one of my designs.
I have a source clock of 100MHZ , but i want to clock something at 200MHZ ( twice the clock speed). Is is possible to generate a part (maybe using core generator) to do this ?
Any help...
Hi guys ,
I am designing a mux, i want the select line to be set to 1 on every rising edge and 0 on every falling edge, that way the mux is changing twice every clock cycle. I seem to be having problems getting this to work, any one have any simple code that will do what i require.
thanks...
how to eliminate framing error
Hi Steve.
Bascially i have set up a serial link between a Virtex II Pro Eval board and the PC , and this board has a MAX 338 chip at RS232 connection so i assume thats the translator chip you ar on about.
How do you know what baud rate you are sending data out...
uart framing error
Hi everyone,
I have setup a uart so that i can transmit serial data the PC. As i am only sending data to the PC,i have just set up a UART for transmitting.
I am using a sofwtare to read the data that has been sent to the PC. The data is not what it should be, and i have got...
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