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Hi,
I am trying to run a AMS Simulation for an ADC. The problem is that some of the signals automatically get deleted from the psf directory once the simulation finishes and so I am not able to plot them. I can plot those signals while the simulation is still running and I have explicitly saved...
Hi,
Can anyone please tell me what load capacitance to use when working on 110nm technology to design an opamp? I remember it used to be 500fF for 180nm technology node. How to determine this value?
Thanks...
The calculator in the waveform viewer in cadence has a DFT function. Use that. You can tweak the values in the required fields to get the desired accuracy...
Hi,
I am designing a circuit using UMC 90nm technology and generated the layout automatically. But I am getting certain DRC errors, some of them being:
i) metal corners should be 135 degrees
ii) vertice not on grid
Please suggest some way out of it.
Apart from this, the DRC rules file had...
Hi,
Are arrays in verilog synthesizable? If yes, then how? Currently I made a long one dimensional vector of regs with a total length of 32768. And the addressing is a bit complex. Also, the RTL Compiler crashes while elaborating my design. It is not showing any error and starts elaborating. But...
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