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Hi All,
Generally, in Band-gap references we do insert a small "ac signal" in between output of Op-Amp & gate terminals of PMOS transistors, for analyzing stability, right?
As we know, output of Op-Amp is the low impedance node.
What ever the small ac signal we are applying will go into the...
Hi all,
Could any one pls explain me, how to derive Error Amplifier specifications from the given LDO specifications?
I have below specifications:
Vin : 2.7-3.3V
Vldo: 2.5
Iload: 0-40mA
Quiescent Current: <50uA
Settling time: 100uS
Line/Load Reg variation: <1%
From these, how can I determine...
"No, opamp output is not (generally) low impedance & it's the loop which makes it low impedance"
Could you please elaborate your explanation on above sentence?
thanks!
Hi All,
Generally, in Band-gap references we do insert a small "ac signal" in between output of Op-Amp & gate terminals of PMOS transistors, for analyzing stability, right?
As we know, output of Op-Amp is the low impedance node.
What ever the small ac signal we are applying will go into the...
Can any one help in solving the below problem?
there is a transmission line with source & load impedance are as shown in the attached diagram in terms of Zo.
Calculate the reflection coefficient of this line at source end as well as at load end.
Plot the voltage (Vout, V1 & V2) wave forms w.r.t...
Hi all,
I designed bandgap reference with the following specifications.
Supply 1.2V
Ref voltage 600mV
Power consumption <10uA
temp coefficient <50ppm/C
Design is completed and met above mentioned specifications.
Now I am doing stability analysis. For this I chose .tran analysis with supply...
Hi,
Can any one explain "Why temp coefficient of poly resistors can be either positive or negative?"
Which resistors like poly, well, diffusion etc will be good to use?
What are the things I need to consider while using passive components?
thank you.
regards,
Subhash C
Hi all,
Can any one share the good documents related to CMOS IO Driver?
also, Can any one explain the practical problems we face in designing CMOS IO driver?
Pl help me in this.
thanks.
regards,
Subhash C
Based on my interview(s), I prepared this document.
pl find the attachment.
Hope it will help you all. At least it will show the path for STA learnings.
Re: [STA] Timing Optimization
First, we will try to fix @ desired frequency only.
As we are moving down, it will be difficult to close the design @ desired frequency.
At this critical stage, we will fix the all hold violations to make sure your design is functionally correct. Then we will move...
By considering which timing (setup or hold) fix, you said the above statement.
If it is for setup, if you insert near to capture flop, it doesn't work. For better results, we should insert at the center of the wire.
In PT shell, you can't see better results if you use "insert_buffer" command...
There are terms called, Negative Skew & Positive Skew, defined w.r.t the direction of the clock & input data coming to the design.
w.r.t above terms explanation for the above problem is given in the attached pdf file. Pl go through it.
regards,
Subhash C
Hi,
tcq + tcomb <= T + tskew - tsetup
T = clock period
So, for the above question, minimum time period is 7ns (its not 5ns).
For setup & max frequency calculation, skew is the added advantage.
regards,
Subhash C
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