Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by Storm7

  1. S

    Active Surge Clamp Operation

    Klaus, I know what V_gs represents. I can subtract the Vs from Vg in the graph I posted above. If you don't have any helpful advice towards my question, can you please refrain from responding to my post in such a condescending manner? Thanks.
  2. S

    Active Surge Clamp Operation

    Well I figured it out...auto-axis got the best of me. I saw the output green line at 0 and assumed it was the Y-axis showing 0V :bang:. Well after extending the Y-axis down to 0V, it's much more clear. Now I'm trying to figure out why there's a ~4V drop across the nfet with its low rds_on.
  3. S

    Active Surge Clamp Operation

    Hi guys, I'm looking for some help in further understanding how this active surge clamp works. The nominal input voltage for the system is 28V and the surge voltage is 80V for 100ms. The output is clamped to ~36V to protect everything downstream. The Vth of the N-FET is 4V. I've ran some...

Part and Inventory Search

Back
Top