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Recent content by stocol

  1. S

    how to do stability analysis for bandgap circuit?

    loop stability analysis on bandgap there are negative feedback and positive feedback at the same time. u can simulate the loopgain and phase margin keeping the feedback loop closed. by inserting a Vac into the location between the output of opa and the gate of pmos mirror u can simulate Gv,and...
  2. S

    layout problem about scaling cap in dac

    yeah i just want to point out that what 'scaling capacitor' means in my design, that capacitor is 32/31 times the size of 1LSB capacitor hi protonixs: 1LSB capacitor is 100fF, and it cannot be divided into 32 parts for the process precision. if i choose a large 1LSB capcitance, the cap array...
  3. S

    simulating offset by monte carlo analysis?

    to simulate offset of a comparator,i use mos transistor model *_mis which is used for monte carlo analysis in spectre of cadence, but i dont know what the 'correlation index' of the input diff pair should be set, anyone knows? and i also want to know how to get histogram thx for ur answer
  4. S

    Voltage Reference Vs. Voltage Regulator

    regulator,i think u mean ldo,serve as power supply. i think what u need for ur adc is volt ref,generally bandgap voltref. it needs trimming to obtain accurrate value
  5. S

    Can the SAR ADC be designed for 40Msps and 12 bit?

    Re: REG SAR adc for a 12 bit 40Msps sar adc ,precision conflicts with speed seriously. piplined adc a wise choice
  6. S

    Successive approximation register

    sar verilog if u generate SAR register by VHDL code, the digital circuit probably redundant. i have seen some paper about nonredundant SAR circuitry
  7. S

    layout problem about scaling cap in dac

    hi all, a charge-redistribution dac is needed in my design. the scaling capacitor is 32/31 times the size of the unity capcitor, to achieve good matching,how to design the layout? ur suggestion appreciated
  8. S

    layout problem about scaling cap in dac

    hi all, a charge-redistribution dac is needed in my design. the scaling capacitor is 32/31 times the size of the unity capcitor, to achieve good matching,how to design the layout? ur suggestion appreciated.
  9. S

    how to simulation the switch cap circuit

    if u make your simulation in spectre of cadence, u can choose PSS+PAC to simulate the frequency response of SC circuits hope it helps
  10. S

    problems about ldo in rf frontend

    i found the reason in today's test the noise on the output of ldo is large and it is amplified even modulated through pll so the pll unlocked when added bypass capacitor to reference voltage to minimize noise pll locked minimized noise furtherly pll locked and c/n improved low noise ldo needed...
  11. S

    problems about ldo in rf frontend

    Hi,everybody i have designed an on-chip ldo for cmos gps rf frontend. when tested, the output from ldo is normal while the pll is not locked-difts around 1.57G. when i used signal generator to supply a stable 1.8V voltage,replacing ldo,pll locked i doubt that the on-chip ldo has too large...
  12. S

    how to simulate the gain and offset of dynamic comparator

    Re: how to simulate the gain and offset of dynamic comparato could u tell how to run monte carlo simulation?

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