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Recent content by stewmal

  1. S

    question about IC designflow

    If you are doing a straightforward digital design you shouldn't need to do spice simulations. If you are doing a digital PLL, DLL, or anything that isn't latch to latch or FF to FF then you might want to simulate with SPICE models. stew
  2. S

    VHDL vs Verilog which more popular?

    I believe that the big EDA companies will lead the push to make Verilog the industry choice. They may support VHDL, but Verilog will be pushed.
  3. S

    Bi-CMOS or CMOS layout - how?

    Re: How many basic layers in CMOS layout besides metels? There can be many variations of the different layers at a Fab. Different Vt's etc.. Read design rule documentation
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