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I myself use inverter chains too in AD design.
I have a question though, has anybody ever experienced problems from too short or too long delays due to process variations?
Interesting topic,
I'm currently trying to get a bit of layout from VHDL to use in my mixed signal chip. Do you have any information or tutorial on either Mentor IC station or Silicon Ensemble on how to do this?
Greetings,
Steve
Using Silicon Ensemble
Hi all,
I would like to find some info or a good tutorial on going from VHDL to a physical layout using Silicon Ensemble.
Anybody have any tips?
Steve
inl dnl histogram method slow ramp
Hi,
I've been dealing with the same problem in MATLAB as well, so I thought I'd put in my 2 cents.
First off, the sine wave in comparison with the clock signal. If you're referring to the FFT analysis, it is important that the sine frequency is not a...
Need help.
Srivatsan,
Have you looked at the ratios between currents? They should be well defined (double W and you should see twice the current). Absolute values are always hard to obtain in IC technology, even in simulations they always end up where you don't expect them.
Current Mirrors
Or if you require a host of currents, you can perhaps determine one common denominator and add unit cell current mirrors. (because of matching issues)
Since the current (at fixed L and Vds) should scale linearly (roughly) with W, I do not understand why the circuit would not...
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