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Recent content by steven23

  1. S

    propagation delay of cmos inverter

    and what if rise time/fall time is greater than propagation delay of a gate, then what will be the clock period? - - - Updated - - - and what if rise time/fall time is greater than propagation delay of a gate, then what will be the clock period?
  2. S

    propagation delay of cmos inverter

    for 2 inverters, shouldn't it be T= 2*2*5ns? because we are considering both HL and LH transitions in one complete cycle.
  3. S

    propagation delay of cmos inverter

    for CMOS inverter, if my propagation delay of a gate is given to be 5ns. what should be the maximum operating frequency for correct output logic level.( if i am having a chain of inverters)??
  4. S

    propagation delay of cmos inverter

    thanks for the reply.it was really helpful..
  5. S

    propagation delay of cmos inverter

    I am totally agree with you..i will put it in another way : when output changes from VOH to VOH/2..and what if VOH/2 is not at logic zero( i mean this value falls in invalid transition region)
  6. S

    propagation delay of cmos inverter

    but shouldn't the output change its logic level after this delay?? suppose output changes from VDD to VDD/2..and what if VDD/2 is not at logic zero.
  7. S

    propagation delay of cmos inverter

    Hi,,I have a query regarding the propagation delay in a gate,propagation delay is generally measured between 50 percent points on the input and output waveforms, why cannot we measure it between 20% or 80% points on the waveforms ? Is there any specific reason for opting 50% points ??
  8. S

    noise margin of cmos inverter

    i am not convinced with this logic..my question is what if we define it at a slope of -0.8 value..is that acceptable value?? one answer comes to my mind is, by defining it at less than -1 will reduce the noise margins, which should be as large as possible( because VIL will decrease and VIH will...
  9. S

    noise margin of cmos inverter

    In CMOS inverter, why VIH and VOL are defined at the slope of -1..why not less than -1.??
  10. S

    Supply Voltage Scaling

    in cmos inverter, if my design requires frequency of 1GHz, what should be minimum supply voltage for correct operation?
  11. S

    Propagation delay of cmos inverter

    thanks. it was useful. does it change the operating frequency of output signal??
  12. S

    Propagation delay of cmos inverter

    In CMOS inverter, what if clock time period is less than 2*propagation delay?? and how to fix it?
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