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Recent content by steve_mac

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    How many of you will be at the ISSCC this year?

    Wondering how many of you will be at the ISSCC this year? Want to make a small EDAboard gathering over coffee?
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    Difference btween APR generated SPEF and RCExt tool gen SPEF

    Hi All, I am an analog engineer, but being pulled in to help in a mixed-sig chip. Hoping the digital gurus here can lend me a hand. Am wondering how much difference is there between the SPEF generated by an APR tool like First Encounter versus a true RC extraction tool like Star RCXT. I...
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    A question of ultresim using.

    first of all, make sure you have selected Tools -> Mixed Signal Options Then Select Hierarchy Editor -> Edit Configuration Then on the Hierarchy Editor select the View - > Properties A new column, sim_mode will appear. Here u can choose the accuracy for the block you are running, from s , a...
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    why ESD protection needn't in test pad and probe pad?

    i think (IMHO) during probing, the wafer is very well insulated. no path for ESD zap
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    Oxide breakdown voltage for TSMC 0.18u process

    nmos2v breakdown Hi folks, I've noticed that TSMC does not publish their oxide breakdown voltage on any of their docs on TSMC-Online. Do you know where i can find this data? -steve
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    Current carrying capacity for TSMC 0.18 process

    thanks !
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    does anyone actually use icstation?

    Just out of curiosity, does anyone actually use mentor's icstation? how good is it compared to Cadence's virtuoso ? i think mentor is fighting an unwinnable battle IMHO
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    Current carrying capacity for TSMC 0.18 process

    Hello May i know what is the common current carrying capacity for TSMC 0.18 metal and poly layers? Both thick and thin metal? If not can someone guide me on where to find it using my TSMCOnline account? Thanks very much :)
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    Suggestion for pipelined ADC layout

    Re: pipelined ADC layout when you layout the reference voltages, make sure they are in the middle
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    Checking for any transistors operating in triode mode

    Hi, Can anyone psl teach me how to check for any transistors operating in triode mode using Cadence ADE? Thanks in advance. :D
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    Spectre issue: how to change the default setting of charts?

    Re: Spectre Problem... Syukri, First of all you need to plot voltage out. then open another subwindow to plot voltage in . then at the first subwindow (voltage out) go to Axes-->X-axis--> and then change the plot vs value from independent to your value (voltage in)
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    What is the coner simulation and how it works?

    Re: coner simulation running corner simulation means running cases with variations in temperature, process parameters and voltage supply.
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    Mentor tools tutorials and other resources

    Re: Mentor tools tutorials go register yourself at Mentor's supportnet. then go to "How-Tos & Tutorials" section have fun
  14. S

    Virtuoso XL Layout editor,who can help me,thankyou!

    do you have cadence sourcelink account? https://sourcelink.cadence.com go register for one of those online trainings (look for those free ones, i.e. not the latest version )
  15. S

    ic design training in australia

    Hi, Do any of you happen to know any good analog ic design training in australia? Thanks
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