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Why are they exactly the same?
Have u deduce the final solution yet ?
Let's check a single pole system,
A(s) = A/(1+s/p) --- Open Loop
I think the close loop should be like this,
(A/1+A)*(1/1+s/A*p) --- Close loop
As u can see,the former part in equation is affected by DC gain.
Maybe there is...
as a instance, u can try to solve step response of a feedback loop other than using a single tone input.
u are supposed to see some difference. DC gain acts as a static settling error in the final results.
It do make sense in a some cicuits e.g. switch cap,anyway,High dc gain benefits the linearity.
u can refer to design rule wihch may include some of the key parameters related to mismatching.
Depending on these, the size of MIM cap can be determined.
Baically, open-loop comp's delay is limited by RC constant.
But, It's a different story for hysteresis comp where positive feedback is generally used.
U can try to find a small signal domain settling time by solving laplace equations.
Unfortunately,comp works in large signal condition most of...
Caps size is limited by KT/C noise, Settling time , Mismatching etc.
U can use these spec. to define reasonable value of caps.
SW is also determined by settling.
steve guo
Re: problem with SAR ADC
what's your bandwidth? How much resolution you need?
SAR is suitable for middle speed and middle sample rate. e.g 10 ~ 14 bit, several Mega Hz
Current is too small,
You can simulate a simple case with diode connected MOSFET and try to get it's gm/ID vs ID curve
280 is too high and I think you should reconsider the accuracy of the model.
From my experience,Model has dicontinuity in extrmely low current condition
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