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Thanks, I see. It's not something critical on my end.
---------- Post added at 09:46 ---------- Previous post was at 09:44 ----------
The software is CSiEDA 5.4 SE. Have you tried this software?
Hi there,
DRC flagged all GND via's with "missing thermal". It was fine as I applied DCR along the way laying out the board, now it's almost done, all of a sudden, this "missing thernal" flag shows up on all my GND via's. Does it have something to do with the ground copper pour being applied...
This is my original question, given small Vds, should I reduce Vgs to place Q1 in saturation region or use a large Vgs (taking out R3) to place Q1 in linear region? Which gives lower Rdson?
My understanding is that: Rds is larger in Saturation region than in linear region. So R3 should be taken...
Sorry I am editing this too many times,
When Control voltage is high: Q2 on, Q1 on.
for Q1: Vgs=-9V, Vds<-3V. My understanding is that for Pfet in saturation, abs(Vds)>abs(Vgs-Vth), assuming Vth=-4V, is this correct? I admit this is getting a little confusion for me.
Thanks for your patience..
Thanks for your reply. This is on/off switch. You are correct, there is senor based feedback loop of the circuitry that feeds the uP, I didn't show.
My confusion is: Vds for PFet is only -3 V, if R3 is taken out, Vgs would be -9V, so PFET is then not in saturation. Since Vds is small, so...
Need help with PFET gate biasing level in Li-ion passive cell balancing.
Hi there,
Please take a look at a Li-ion balancing circuit, what gate biasing level should be chosen?
The question really is should the PFET be turned on in saturated region or triode region?
Thanks in advance.
Hi there,
Please take a look at a Li-ion balancing circuit, what gate biasing level should be chosen?
The question really is should the PFET be turned on in saturated region or triode region?
Thanks in advance.
Thanks for your reply. I thought when using mosfet as switches, usually they operate in saturated region, Vds and Id are determined by the load line from the circuit. Am I missing something? Could you elaborate? So Rds(on) only applies in non-saturated region?
Thanks again for your help.
I have always tried understand the consistency of Id in many mosfet datasheets, I must have missed something.
For example in the datasheet I attached Si1422dh,
From the top in the Product Summary box, it lists 4 Rrs(on) values, with Id at 4A at given Vgs levels.
However, looking at the...
There are several copper fill options in my layout design package, could anyone give a plain English description of them? I put in my 2cents in the ones I used. Thanks in advance.
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*************************** Copper fill options...
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