Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
lylemalone,
I'll throw in a couple of quick suggestions, and the community will probably throw in several more good ones:
1) in your sensitivity list, make sure the edge event always blocks do not have unnecessary signals
2) it is best practive to put non-blocking statements in edge-triggered...
Perhaps the syntax of the for loop should mimic verilog's syntax contraints for incrementing:
for example:
//synthesizes
count_reg <= count_reg + 1;
//fails
count_reg <= count_reg++;
//for loop syntax
for(i=0; i<N; i=i+1) begin : GENERATE_VOQ
I created this ascii art to put in my verilog code near any tristate instances to remind myself visually what is occurring....
keep in mind, this should be used with mono-spaced fonts, it will not make sense without one....enjoy...
When I first started out in digital design, I used the following books as Bibles:
1) Advanced Digital Design with the Verilog HDL
2) FPGA Prototyping By Verilog Examples
That being said, I used the published papers by Sunburst Designs to learn/experiment with advanced topics such as clock...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
