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Recent content by ssudhasa

  1. S

    PhD in Digital VLSI- Help Reg

    phd vlsi Which university is good for Phd in VLSI Design , gives full scholarship
  2. S

    FIFO Depth tricky question

    fifo depth question Can you elaborate more on this.. In my point of view the fifo depth should be 16.
  3. S

    Multiclock design(Argent)

    Hi Please help.
  4. S

    counter value detection using edges

    Thanks for the discussion. I agree, you r right.
  5. S

    Is the circuit correct for positive edge detector ?

    positive edge detector Hi, I have one doubt.. is the circuit below is correct for postive edge detector when even occurs.
  6. S

    Multiclock design(Argent)

    Hi, I have a question. CLKA = 2 × CLKB Signal in CLKA domain is active for 2 CLKA cycle. At clock domain crossing we have used 2 bit synthronizer, At synthronizer output, how many CLKB cycles it will have . ?? options: (1) 1 (2) 2 (3) 3 And Also , for this MCD scenario, 2 bit synthronizer...
  7. S

    multiclock design(Argent)

    Hi, CLKA = 10 × CLKB CLKB= 10MHz, how many clocks of CLKA is required to transfer the data in 1 sec. ?
  8. S

    counter value detection using edges

    okay ! that is for 15 --> 0 detection. BUT for count 2-3 ? 0000 0001 0010 2 0011 3 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
  9. S

    counter value detection using edges

    Hi, Thanks for the reply. My question is : if i have to communicate the count of the 4 bit counter to the other clock domain, the domain. the follong circuit is correct for 15-0 detection OR it should be posed detection at the AND GATE .
  10. S

    counter value detection using edges

    Hi I have problem: question: 4 bit binary counter(0 to 3) , counts increments from 0 to 15 in clock A domain. now the count has to be communicated in the other clock domain clock B using edge detection circuits. what will be the ciruit will it use to detect count 2-3 . & what will be the...
  11. S

    metastability- settling depends upon MTBF or something else?

    metastability FF goes metastable , will sattle after some time to either 0 or 1 . this depends upon . MTBF? or some thing else ??
  12. S

    FIFO Depth tricky question

    min fifo depth same frequency different phase Thanks for ur reply. thats true, if i take this approch i will get the FIFO depth of 16? since the frequencies are same i do not need to put the synthronizer, hence synchronizer latency (usually 1 clock cycle)will not be there Thanks in advance,
  13. S

    FIFO Depth tricky question

    fifo depth design Hi, I need to provide the delay of 16 clock cycle, using FIFO. if write frequency and read frequency is same and phase is also same, then FIFO Depth should be ? options are : (1) 16 (2) >16 (3) <16 Thanks for anticipation !!
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