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Recent content by ssti85

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    Gate Induced Drain Leakage (GIDL)

    Hello, Can anyone please explain the phenomenon of GIDL? I am basically looking for its behavior in sub-threshold region. I found the reference in a book where it says - the effect occurs for high CDS values in combination with low VGS values. It would be great if someone could explain this...
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    test bench in vhdl for set up & hold time violation

    its not very difficult to do that. You must have written normal test benches. Just put that in a for loop. and repeat the loop certain number of times (say a avg value of 1000 or so). Plus, in each iteration, try to take a different set of inputs. This usually should be done, so you get a...
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    test bench in vhdl for set up & hold time violation

    First of all, you must use the synthesized netlist, and not the actual verilog/vhdl file you must have written. Second, you must have a rigorous input vector of all possible input combinations. Something to be highlighted here is that the testing must be exhaustive - which means, many...
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    difference between LV_ and LX_ paprameters in mosfet model

    Hello All, I have a really basic question. Does anyone know the difference between the LV_ and LX_ parameters in a MOSFET model?? By looking at the model, I can intuitively understand that the LX_ parameters are detailed as compared to the LV_ parameters. Thanks
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    Power Analysis in Encounter

    Hello Research235, Thanks for your mail. For now, I am able to get the reports using Encounter. Although, do you know - what is the difference between update_power and report_power in encounter? Thanks for your mail again. Ssti85
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    Power Analysis in Encounter

    Hello, I'm trying to do power analysis of a circuit. I already have a .sdf and .vcd files. When i do report_power, it would only give me the leakage power in the log, but no switching power... I'm looking for finding switching power through .vcd file. Thank you.
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    Difference between hard macro, partition block and black box

    Re: Difference between hard macro, partition block and black Hello rca, Thank you for your reply. I'm actually working on a layout that also has a memory block as a hard macro, and use foundation flow scripts which I'm also editing for my application. I was struggling with the placement of...
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    Difference between hard macro, partition block and black box

    Hello All, What is the difference between hard|soft macro, partition block and black box. Also, when we talk about the placement status of a block, what is the difference between placed and fixed? Also, what is 'cover' in the same context? I understand that 'unplaced' will allow the macro...
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    How to caliculate Leakage Power in Cadence

    finding leakage current wasnt easy for us as well... althoughh, there is one post on edaboard.com that suggested that one method is to cut all inputs (ie effectively keep all the devices switched off manually) and then measure the current flowing through the supply. Its not the best way of...

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