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thanks for your reply sharath.but where exactly in the prime time tool to provide this constraint .
If you have any video lecture links or pdf kindly send me the link
How to perform Static Timing Analysis using Synopsys Prime Time?
when i try to find STA i am getting the following error message
"No constrained paths"
I need to find the worst case delay in a circuit sat alu4 or c7552,c3540 etc.
Can anybody please help me??
How to perform timing analysis for MCNC benchmarks?I have circuits in BLIF format.In general i want to know how the timing analysis is carried for LUT based circuits?
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