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Can you explain a bit more about your circuit- as in beahviour?
Is there any clock in your circuit.
What are there DC input? Step inputs? If so how and when do they get triggered?
NANOSIM help
Hi all,
I have a clocked circuit that accepts 8 bit input and produces a 8 bit output.
Say for example the clock is running at 2.5Mhz.
For a given 8 bit input vector I want to measure the power consumed by the circuit in one clock cycle at a rate of 1Ghz.
That is to say take...
Gate Equivalent
Hi all,
I am designing an ASIC. I wanted to calculate the Gate Equivalent for the same.
Could someone explain me how to do this.
Thanks
Saurabh
Re: How to synthesize generated clock in cadence RTL complie
hi navneetgupta,
Yes indeed I can synthesis the ckt by just defining clock. But that produces unconstrained results for me.
The Sythesizer fails to understand that the signal generated by...
Libraries for Cells
Hi all,
Could someone explain me the meaning of the following statement that are present in cell libraries.
1. Next state functions
2. Foot print statement.
Thanks
Saurabh
Hi, could you describe these librarys and where to use them（in which tool）
1. tlf
2. lef
3. def
4. lib
5. db
6. cdb
LEF- Has info abt metals via contacts. Used in Place and Route, Synthezier. Also needed in parasitic extraction if you are using Star-RCXT tool.
LIB- Has all cell timing info...
Re: How to synthesize generated clock in cadence RTL complie
Sorry for my lack of knowlege. i am not that well versed with Synthesizer. Could you tell me what is that you mean?
Hi all,
I have a verilog structural net list that, besides having all sorts of logic gates and ffs, it has a number of macros described as timing models by a separate *.lib and *.lef files.
Functions represented by our macros are complex sequential functions. Too complex to be...
pll verilog hdl
Hi all,
Does anyone have any idea how to synthesize a generated clock?.
What i have is CLK2 and CLK1.
Clk1 is global clock.
Clk2 is generated using CMOS logic. Inputs of this CMOS logic comes from gates that use CLK1 as their clock.
What I am trying to build is a...
Hi all,
Does anyone have any idea how to synthesize a generated clock?.
What i have is CLK2 and CLK1.
Clk1 is global clock.
Clk2 is generated using CMOS logic. Inputs of this CMOS logic comes from gates that use CLK1 as their clock.
What I am trying to build is a self timed...
Hey hi,
A Standard lib contains a complete list of cells as already mentioned.
All these cells are defined as timing models, written in such a way that a synthesizer can understand.
In order to build a lib, first you need to make layout of all the cells that you plan to include in...
what is calibre
Hey All,
It was a license issue. i havee got all my issues cleared . Star-RCXT and calire work very well in sink. If anyone has issues with the same can surely contact. I have done some good amt of field work and will be able to answer certain questions.
Thanks Again
calibre query
Hi all,
I wanted to know what excatly does Calibre Query server do.
When I run the command:
$MGC_HOME/bin/calibre -cb -query extractRunDir/LvsRunDir/svdb/ < extractRunDir/LvsRunDir/calibre.query.ctrl
The error message that I get :
// Starting time: Thu Aug 13...
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