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hello people.........
just a small and humble request to u all........
i appreciate the willingness of good people here to help others. but i am finding that, in the enthusiasm to help others some are giviing out the paths to the softwares publicly. if someone from those company is wacthing our...
hello people,
i want to know the difference between
- D/F/T/ C/o/m/p/i/l/e/r
- S/o/C/B/i/s/t
- T/e/t/r/a/M/A/X A/T/P/G
- T/e/t/r/a/M/A/X T/e/n/X
- T/e/t/r/a/M/A/X D/e/l/a/yT/e/s/t
which one is the best among these? does all these tools are same? please guide me
SSS
hello people,
i want to know the difference between
- D/F/T/ C/o/m/p/i/l/e/r
- S/o/C/B/i/s/t
- T/e/t/r/a/M/A/X A/T/P/G
- T/e/t/r/a/M/A/X T/e/n/X
- T/e/t/r/a/M/A/X D/e/l/a/yT/e/s/t
which one is the best among these? does all these tools are same? please guide me :-)
SSS
hi,
i came to know that u can get those s/w from anonymous login also....but when i tried that "ls" command did not work!!! may they are hiding those s/ws. i hope many in our group knows the path and name of the softwares in that ftp site. i request him/her sincerely to provide those links for...
cordic algorithm
hi all
can any body here explain me what is cordic algorithm, where and why is it used? any useful links are also welcom. i tried google, but the links were not in simple english :(
thanks
srisrisri
why hold time negative
hi
there are some flops with negative set up . they are called as hybrid flip-flop(if i correctly remember!). it internally has an edge detection circuit and delay and then a flip flop. the delayed edge is fed to the internal flop and hence we get -ve set up. but i have...
what is meaning of negative setup and hold time
hi
there are some flops with negative set up . they are called as hybrid flip-flop(if i correctly remember!). it internally has an edge detection circuit and delay and then a flip flop. the delayed edge is fed to the internal flop and hence we...
hi all,
as the name of the topic indicates, i want to know the difference between the stray capacitance, parasitic capacitance and coupling capacitance with ASIC as the referance. can any knowledgable person explain them to me?
thanks for listening to me.
SREE
i have a doubt to share with you all...
we can convert .syn file to .db by using library compiler.
but how can we get .syn or .lib file from .db?
is there any tool to do this? if so please share with us or pm me
thanks anyway!
SSS
hi stevepre
after trying for Synplicity and FPGA express, i gave a try for synopsis DA. Interestingly i found that by setting one of the below variable(i don't know exactly which one) we can get the port in the way in it was in the original code.
vhdlout_preserve_hierarchical_types = "USER"...
hello everybody
i am facing a problem with type array of array. below
i have given a simplified version of the problem
--package my_pak
type my_typ1 is array (0 to 1) of std_logic;
type my_typ2 is array (0 to 1) of my_typ1;
--entity declaration
use work.my_pak.all;
entity ...
hello everybody
regarding the FPGA synthesis, we can think about
various tools like FPGA express,Leonardo Spectrum or
synplicity tools. but the question is.. which of the
presently available tools is the best of all? i hope
that the experts who have worked on these tools can
give a comparative...
hi all,
i am a beginner to ASIC. I came to know that the libraries used for synopsys are in db format. but when i tried to view them i could not make out anything! may be it was encrypted. but *.lib files are simple ascii files. so by any chance can i get back *.lib from *.db? if so please guide...
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