Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi,
if the clock frequency is exactly equal to (setup+hold) time duration then the FF and latch.
Thanks & Regards,
Sri.
Added after 1 minutes:
Hi,
if the clock frequency is exactly equal to (setup+hold) time duration then the FF and latch are same.
Thanks & Regards,
Sri.
Re: clock dividers
Hi,
T-FF will be a clock divider.
Input to T-FF is logic-1 always
Output of T-FF is always toggled w.r.t input clk.
the frequency will be half the input clk.
Thanks & Regards,
Sri.
hi,
i am quit new the linux environment .i need information regarding how to run the perl file in redhat linux 7.2 . is perl software is inbuilt or i have to ldownload from the net and load the software.
if possible give me command for rnning the perl program in linux.
thanks...
hi,
how we can go for regression testing in case of specman elite what will the procedure to follow.
with regards,
srik_naidu
Added after 3 minutes:
hi,
here what will be the batch mode.can anyone give me an idea how the process will be.
thanks in advance,
with regards,
srik.
hi all,
i need information regarding regression testing.these are my doubts, what will be the regression testing,when can we use that particularly in case of using specman elite .
thanks in advance,
wth cheers,
srik
ASICs Vs FPGAs
hi,
in case of fpga alot area is wasted but in case of asic it is not like that.
fpga is reprogrammable but asic is not.
with regards,
srik.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.