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Hi,
I have a rule in calibre that need to be converted into assura drc.
Please help me.
VIA1.R.2_FSG { @ When M1 or M2 width > 1.4um, more than 1 VIA1 is required.
@ if the metal has < 4 vias, vias spacing should be <= 0.71um,
@ or if the metal has >=4 vias, at least 4 vias...
Hi,
I'm trying to draw layout for photo diode in umc180 um process.
but there is no device model even in the design document. All i have is photodiode sensor related drc rules.
Please help me to draw a photodiode.
Thanks,
Sree
antenna is taken care by metal jumpers or reverse biased diodes.
preferred method is metal jumper.
you can put a single substrate contact in parallel to the net that is getting antenna violation in order to get rid off antenna ( this works as reverse biased diode)
antenna is something that happens while getting fabricated
esd occurs after chip gets fabricated when a machine/human body touches the IC.
hope this is useful
Hi All,
I am able to run assura drc without any errors but it is not listing all the errors. It is just listing density errors. but when i checked in rules file all the rules are there in rule file.
can anyone say what might be the problem?
Regards,
Sree
You can try using nwell or poly inorder to get resistance.
create a layout for resistor and also spice for R=100ohm and run lvs keeping A & B as pin names for resistor ends(both in schematic and layout).
You can get the resistance value from the lvs report. ( it will show parameter error and...
single substrate
substrate is all the way same for pmos and nmos.....
we just have nwell implantation in order to get pmos.
they are trying to be bit tricky it seems
or they use pwell in nwell(not sure abt this)
even i have the same doubt....
one more thing is "some technologies prefer rectangular vias than square vias, where as using 2 square vis is preferred so far I know"
can any one explain?
Regards,
Sree
Re: Common practices of a good analog and mixed Layout Desig
shielding is a process where you put the metal line to be shielded in the middle and both sides you draw a path with same metal and cover the three lines with top and bottom metals with all the four drawn layers connected to VSS or GND.
Hi All,
I'm doing a test layout in UMC 130 nm process.
An NFET substrate is connected to net "V6" where as all the other NFET's bulk is connected to SUB.
I dont even have design rule document with me.
Can any one say which is the layer to be used for isolating two substrates.
Thanks,
Sree
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