Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
layer adjacent trace pcb
Thanks--I just spoke to Prof. Tom Van Doren (the master of all grounding/shielding issues) at Missouri Institute of Science and Technology, and he confirms what you said. I didn't understand the reasoning, but he made it very clear. The reason is because for high...
trace impedance
Hello,
I have a multilayer board (12 layers, might have to increase...read on) with multiple isolated grounds (returns).
It is an FPGA design, and all of the signals with critical impedance specs are FPGA-ground referenced digital I/O signals.
In my layer stackup, there are...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
