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Hi all,
I am using xilinx ISE 14.7 and spartan 3e
The part of my VHDL code where I got error is::
if (kk<=x"010000")then
bh := x"00";
else
bh := x"01";
end if;
where
variable kk: sfixed(22 downto -1);
variable bh: sfixed(6 downto -1);
and packages used are::
library...
Thank you for the information.
As you said, I got delays., it took more than one clock cycle for the operations that I assumed would be done in a single clock cycle. Can I know the reason for it taking an extra cycle.
As far as I searched, I got to know that PID contrllers were designed on...
Hello,
In converting (22 downto -51) data to (7 downto -8) data, 15 bits of decimal part should be removed. By doing this the actual value cannot be approximated to the nearer value.
For my application this percentage of error is more. Can you help me to reduce this approximation...
Hello all,
I am trying to design a digital PID controller using Spartan 3e FPGA and VHDL coding.
I used sfixed data. Initially I assumed input, delayed output and system_output to be sfixed(7 downto -8). After arithmetic operations I got the output c(22 downto -51), which I...
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