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Recent content by sougata_vlsi13

  1. S

    use of cordic rotation method to implement FFT in VHDL

    Hi,I have started with the FFT implementation using cordic in xilinx FPGA.After referring quite a good number of pdf's and thesis report i got a view about the designing but the main context i need a proper block diagram along with the i/p and o/p signals.Please if anyone has a proper block...
  2. S

    LDPC decoder project of Open cores in verilog

    I am done with the LDPC FU part as well as the controller part of the design as specified in the above mentioned thesis report.Now in the main block diagram it is given that the controller is controlling the total unit along with the shuffle network and decoded message.I just want to know how...
  3. S

    use of cordic rotation method to implement FFT in VHDL

    Hi,I have implemented radix2/4 & split radix FFT algorithm without using cordic.They are running fine...o/p is coming but the problem is that the code is non synthesizable.To make that code synthesizable i have to implement cordic and need to interface it with the FFT code.I read few documents...
  4. S

    Use of SXT function in VHDL

    Can anyone please tell what is the use of SXT function in VHDL.I have searched in the net but not able to get a clear idea about that
  5. S

    [SOLVED] Implementation of Radix 4 FFT in VHDL

    sir i want to verify as what i was manually calculated in pen and paper...The code is working fine for me in case of radix 2 and split radix since i have to use signals which only drives single expression but here in this case it is driving three expression thts the issue...actually i want...
  6. S

    [SOLVED] Implementation of Radix 4 FFT in VHDL

    yes sir i agree with u... i am m using them only for testing purpose but how should i remove that error shown above in the ISE bcoz otherwise i had to forcefully drive that signal 3 times in which check syntax is ok but nthing but a problem of multiple driver.
  7. S

    [SOLVED] Implementation of Radix 4 FFT in VHDL

    IEEE.MATH_REAL.ALL;this is the package - - - Updated - - - type complex is record r : real; i : real; end record;this is used for complex functions
  8. S

    [SOLVED] Implementation of Radix 4 FFT in VHDL

    since i am dealing with the complex arithmetic...so for that purpose i use add function which is declared in the package...not only add i use sub and mult also which are used for subsequent operation.these functions are useful for floating point arithmetic.I have use only one packge which dealt...
  9. S

    [SOLVED] Implementation of Radix 4 FFT in VHDL

    I am using xilinx ISE 14.1 and i am getting a problem with the operand and multiple driver while implementing radix 4 FFT. the problem is that g2(0) <= add(s(1),mult(s(5),w(1))); g2(0) <= add(s(1),mult(s(9),w(2))); g2(0) <= add(s(1),mult(s(13),w(3))); from g2 actually there are three...
  10. S

    conversion of negative floating point in binary using VHDL

    yes i read that article...i know about the representation but i dont know how to remove that decimal point while writing it in vhdl bcoz if i write with the floating point the code is going to be non synthesizable
  11. S

    conversion of negative floating point in binary using VHDL

    I was literally stuck witha problem regarding the conversion of negative floating point in binary and to write it in VHDL.For example the num is -0.8.when i convert it into binary it is like .11001100.since it is -ve i have to convert it into 2's complement and to provide the extra MSB bit...
  12. S

    Split radix FFT algorithm

    I have implemented radix 2 and radix 4 FFT algorithm but without using cordic.Now i moved upto split radix..problem is that i am not getting a proper flow diagram such as a butterfly structure as in radix 2 and radix4...can any one provide any good related document for this and what is actually...
  13. S

    LDPC decoder project of Open cores in verilog

    please anyone help me with the above doubt...i am eagerly waiting for reply
  14. S

    LDPC decoder project of Open cores in verilog

    @ mina magdy and others I studied that thesis report according to the pdf of the "MSc_thesis of LDPC" and also understood the code about the VN_CN update provided by you.I think some part of that code is wrong which doesnt correspond to the functionality. first of all the signal "reg [6:0]...
  15. S

    LDPC decoder project of Open cores in verilog

    I got my answer about fixed point...but will this design of LDPC be fitted into the FPGA bcoz i think too many resources are utilizing...
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