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mos varactor substrate current
Can someone explain when I should be concerned about substrate current when using a mos varactor? And what kind of simulation should I run to test this? Thanks.
Is anyone familiar with measuring the loop gain of a voltage regulator using a network analyzer? I've read about several methods using an isolation transformer to inject a floating voltage into the loop. My problem is that I don't have an isolation transformer.
Here is a pdf explaining the...
I cannnot pass Calibre LVS on my APR block when the environment variable PEX_RUN is set to true. The design does pass lvs when PEX_RUN is set to false, however. Does anyone know why this might happen? Also can someone explain what the PEX_RUN environment variable does?
I want to set a specific hold time for my design in SoC Encounter. Is there any difference between using" set_clock_uncertainty -hold" and "set_min_delay" to do this? If so, what is the difference between each command? And which is better to use?
I'm a beginner at using Encounter and am running into some issues. The timing analysis reports in Encounter show no setup or hold time violations in my design. However, after I import the layout into Virtuoso and run a simulation on the PEX extracted view (R+C only), there are several violations...
Does anyone know how to report the capacitance at a particular net or port in SoC Encounter? Also, how can you set the capacitance limit for a particular net/port? Thanks
I am getting hold time violations when simulating a design in NC-Verilog. The error message looks like this:
Warning! Timing violation
$setuphold<hold>( posedge CK &&& (flag == 1):120 NS, negedge D:120 NS, 1.000 : 1 NS, 0.500 : 500 PS );
File: ../synth/ibm18.v, line =...
Do you mean the the library with my standard cells? If so, I have a '.v' file associated with all the standard cells and also the normal library with schematic, symbol, and layout information for all the standard cells. Which one are you referring to? And also, how would I import it? Thanks.
It...
I am currently having an issue with ncelab when using ncverilog in Virtuso. I keep getting error messages like the following:
nfetx M1 ( .S(cds_globals.gnd_), .G(net11), .D(Y),
|
ncelab: *E,CUVMUR (./ihnl/cds0/netlist,18|8): instance 'test.top@counter<module>.U31@AND2X1<module>.M1' of...
After routing my design with nanoroute and running verifyGeometry, I get multiple mincut via violations. I tried setting the number of cuts to two and this fixed some of the violations, but I can't seem to get rid of all of them. Does anyone have experience with this? Thanks.
Here is an example...
Re: DRC Error: NW tiedown
Dgnani,
Thanks for the help. One more question though. When I place an RX rectangle that is partially inside NW and partially not, I get this DRC error.
RX Nwell contact within NW (Where the RX Nwell contact straddling NW is prohibited) >= 0.0um.
I'm not quite sure...
I am using IBM .18u technology and keep getting this DRC error related to my nwells and have no clue how to fix it.
DRC error message:
(((NW not cover by GRLOGIC) or (NW touching BB)) touching ((PC over RX)) not over DN
must be tied down by the time M1 is complete.
valid tie down 1 : pdiff in...
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