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Recent content by songjunjian

  1. S

    How to do static and dynamic test for an ADC?

    Re: about adc test need do dft , and calculate the bit num of adc and signal/noise
  2. S

    THD-cadence simulation

    cadence calculator thd after simulation, select a wave , and then select thd in the calculator, then you can print the value of thd
  3. S

    Can spice simulate Switched-Capcitor circuit precisely?

    i think it depend on the model you use, and the time will be long
  4. S

    Designing a bandpass elliptic filter

    design elliptic filter I think you should search an transfer function , you can do this by software tools, such as fdatools. then you can map the transfer function into circuit.
  5. S

    question about OPAMP offset

    offset is important , so some pipeline adc use calibration tech to decrease the offset of adc .
  6. S

    help for good understanding of analog concepts

    analog concept I think the book by Razavi is good ,design of analog integrated circuit.
  7. S

    differential amplifier to signle ended amplifier

    Add differential end to single end circuit , may be you can use current mirror
  8. S

    Analog extracted simulation

    you can revise the netlist and add the net to list of plot
  9. S

    Help for output stage for analog circuit

    you can read P.R.Gray , analyse and design of analog integrated circuit.
  10. S

    simulating the settling time of "FDA with SC-CMFB"

    how can simulate settling time the switch cap circuit should have twp phase , so your opa should be set the op during one phase , and you can add step signal and simulate the setting time by tran.
  11. S

    some questions about LDO

    The VTH will be larger than the 5v device , so the chip size will be larger than 5v does
  12. S

    Library characterization script

    Re: Library characterization The library characterization use the spice like simulator to extract the information of timing. include rising time , delay falling time , etc
  13. S

    Looking for a PLL model in Verilog

    Re: [req] A PLL Model may be you can get it from the sample of cadance, there are some example of pll.
  14. S

    How can I get TSMC 0.35 ESD and PAD layout?

    Re: TSMC 0.35 ESD you can get it from tsmc , but it is too big.
  15. S

    how to compile BSIM model

    you can compile it with gcc, there are make file ,you can use make command to build it.
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