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I am going to design for Asic.
I learn GUI now and try to start with writing my own script to get the timing report.
I need to know based on what informations i can constraint the path in the design
to start synthesis
Dear all. Could anyone please tell me what kind of informations of the design do we need when we want to start a synthesis for a design? Or to start writing a script for the synthesis?
Thank you very much! :roll:
SoC and Asic
Could anyone please tell me what is system on chip (SoC) design? And the diferences in between Asic design and SoC. Are they the same thing?
Thank you! 8O
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