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Re: About Sandisk
They came to recruit students for ASIC design....but test questions were completely related to analog.... like amplifier gain ..resistance and all....it was quite tough....
how can we take out around 170 bits output at one stroke... shud we stop processing for time bein usin enable/disable signal and then take output thru serial/parallel port to PC or is there some other way....
i am using virtex 4 board.... i have one complete matrix o/p stored in block ram...i want to read at certain interval of time to verify the answer.... how can "readback capture " can be performed ???? wat tool is required...
Can anyone tell me whether is there any provision to know the values stored in block ram at every small instant of time thru serioal or parallel port without outputtin the values during testin input after synthesis in FPGA....
What wil happen if the power supply in the CMOS inverter are interchanged....i.e.,if Vdd is connected to source of NMOS and GND to PMOS source.....
I feel it will work at subthreshold region only....What is your views....
Can anyone provide me C(or C++) code for parallel/serial I/O port connection with Xilinx board using communications port(COM1/COM2) port of my computer...
or can anyone provide me with the pdf for communications port in PC which gives details of address of each reg/port inside....
Time sharing and time borrowing is the significant adv for latch in case of robust design.....But still latches are not prefferd over FF....
Using JK FF we can implement many function with lesser number of combinational gates...thus lesser delay....whereas with D FF size of Comb block will...
Thanks Darock,
But u see in M-QAM ...LSB bits are coded with ASK and MSB bits are coded with PSK...so there is lot of diff....as we know that PSK has min probability error....
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