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Thank you for answering t4_v.
It didn't work. I agree that it's strange! Maybe because I'm using an old version. Have you ever used this source with reference other than GND?
Thank you so much for answering Timof.
"screenshot.png" shows the file which works without any problem. When I change it as "screenshot1.png" an error is shown saying no such file or directory. I tried wiring the negative node of the source to CHIP_GND directly. But nothing changed.
Hi everyone!
I am using vpwlf as an arbitrary source in cadence. I simulated my circuit using this source without any problem. Then, to consider some parasitics, I added an inductance in series with GND. Now I get the error: "no such file or directory". I know the problem is using a reference...
Hi everyone!
I need to know the Drain to bulk breakdown voltage of CMOS 0.18um technology, but I couldn't find it in the pdk, there is nothing even about junction breakdown of diodes! does anyone know the VBD of drain to bulk or some estimation of it?
it is always said that the drain voltage...
Ok, as I understood you want the branch to be high impedance @ RF freq you are working at.This series LC has got a zero, so it will act like a notch filter for the resonance freq. it seems the resonance freq is far below the RF freq which means it is not gonna change the behavior of your...
The impedance seen will be different this way. for a single C impedance @ f=0 is infinity and decays to zero as freq increases but for an LC it is infinity @ f=0 and f=infinity and zero at the resonance freq of the LC. so if you cared about all these differences and they're not gonna change the...
Hi everyone!
I'm trying to run a transient simulation in cadence and plot the output, but after finishing the simulation, I can't plot any node and an error of "unable to allocate memory.." is shown. Now I want to save the data from simulation to use it in matlab and draw the plots there.
Does...
Hi everyone!
I'm trying to plot the result of a post layout simulation in cadence, but after selecting a node, cadence stops suddenly and this error shows up in terminal:
ERROR: unable to allocate memory for transition file slice variable transition index level (read)
what is it? I know I have...
Hi everyone!
I am trying to layout a common centroid diff pair as below:
GND D1 S D2 S D1 S D2 S D1 GND D2 S D1 S D2 S D1 S D2 GND
GND D2 S D1 S D2 S D1 S D2 GND D1 S D2 S D1 S D2 S D1 GND
but i need help connecting the gates and source and drains such that the layout becomes symmetric!
can...
I haven't worked with UMC0.13u, and it seems a bit different, but I think you must connect your P-substrate to ground with metal contacts.
take a look at this:
https://www.edaboard.com/threads/355094/
Hi everyone!
I'm thinking if there is a capacity for maximum current allowed to flow through a device of ratio w/l, like the one for metal layers?
I mean if I have a device which should carry 100 mA, is there a minimum w/l for that? think the device is not biased and will be used as a switch. Is...
Thank you again for answering and the article! But still, I think, this is the DC current which leads to electromigration, As it is mentioned in the article:
" However, one must realize that Joule heating is caused by root mean square (RMS) current and not by the average current, as is...
Hi every one!
I want to layout a PA in CMOS, I know the maximum current density, allowed for the lines, my question is that, should I choose the line width for the DC current or the peak current?
If the answer is peak current, then should I be careful for high currents at the start of the...
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