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Recent content by snake_eyes

  1. snake_eyes

    Looking for UTMI+ specifications

    Re: UTMI+ specification Does anyone have UTMI+ 1.0 (Final revision)? can someone point the link or upload it?
  2. snake_eyes

    Higher Speed design problem

    I agree with BULX, jumping from 100 MHz to 900 MHz is nearly impossible just by re-run given the fact that the silicon technology is same or nearly same. Icreasing frequency to that much level may require re-design even some architectural changes in the design. Achieving 900MHz on FPGA is not a...
  3. snake_eyes

    Which TCL command in Modelsim opens Leonardo spectrum?

    Re: Which TCL Command? @vncvcc, refer to respective tools user guide for the TCL commands....
  4. snake_eyes

    How to detect the second one in a serial bit stream

    bansalr, You will have to sample the serial stream with a clock. Make sure that the sampling clock frequency fulfills the Nyquest's criteria. You can make a simple state machine to detect any sequence then... Please give me some more specific info about your problem and we can work towards the...
  5. snake_eyes

    Where can I get the schematics for ALU?

    Re: ALU @vreddy, Can you specify indetail what kinda ALU you want.. Width of operands, number of operands, operations done by ALU etc...
  6. snake_eyes

    state diagram to check whether a serial data (msb first) is

    Re: state diagram to check whether a serial data (msb first) Its a typical digital design interview question. The catch here is... if the length of the incoming serial stream is not fixed then it is impossible to find whether number is divisible by 5 or not. It is so because the division...
  7. snake_eyes

    which is the best tool for formailty checking

    And seconded!!! I founf Conformal better than Formality.. However many people differ with my opinion...
  8. snake_eyes

    Help:about perl script

    Steven852, Its not that easy!!! He wants the module heirarchy out of a single netlist file. We need to put some nested loops to get into each hierarchy and print according to hierarchy. Also, he needs the port list with each module!! I guess its too much work to be one for free of cost :D
  9. snake_eyes

    Why we add pull up resistor if a 3.3V output signal is driven to 5V logic?

    Re: query Can you describe your problem in detail? I didn't get anything of it!!!!
  10. snake_eyes

    Need some FAQs on VLSI

    Re: FAQ's of VLSI Search www.google.com You will get a lot of websites!!
  11. snake_eyes

    FPGA implementation in PCI express Using Verilog/VHDL

    pci express vhdl choonlle, What do you want exactly?? You want info about PCI express and some verilog code. What verilog code you need?
  12. snake_eyes

    Looking for Verilog code for RISC processor

    Re: verilog code geez!!! You want an optimized and good RISC processor for free????? Get a life!!
  13. snake_eyes

    Can't assign gclk pin to input clock in ISE 7.1

    Re: input clock problem Pahol is right!! In some FPGAs there are special pins which are reserved for the clock. The FPGA tool will always try to map to that pin. Noiw if the pin 77 is a high fanout global signal pin and the tool is not assigning clock to it, then check if you are using the...
  14. snake_eyes

    What do 'If-Else' statements synthesize to?

    Theoratically all the above discussions are correct. But as I said "theoratically"... If you are using a decent sysnthesis tool, it will optimise the logic in a very good way. So you may see some part of the logic implemented as mux and some may be as preority encoder. The tool basically goes...
  15. snake_eyes

    References about timing closure

    Re: timing closure Refer to your synthesis tool documentation. I will try to get Synopsys DC tutorial for you.
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