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Recent content by snaityma

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    Dracula generate lpe netlist question

    dracula lpe spice To use Dracula to generate lpe file. The output netlist for resistor description like R1 Z VSS NP 100 The NP is resistor layout type. But that is not a correct spice format netlist. How to get correct spice format netlist for simulation with Dracula lpe tool? --
  2. S

    GDS to Star-RC extraction

    gdsii extraction Hi , Can we use GDSII file only to Star-RC for parasitic extraction?? Can anybody know how to do this? Thanks.
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    Dracula LVS says "Segmentation Fault"

    In the end of PRINT.OUT file, are there abnormal info. at summary report, like box number, nmos/pmos type number., etc? OR Did you wirte Dracula LVS command file by youself? Do you specify text file in dracula lvs command file? Maybe you need to check LVS command file description.!
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    Dracula LVS says "Segmentation Fault"

    Hi, Did you check PRINT.OUT file after executed LOGLVS utility ? Maybe, there are some error messages there. OR, any error report when PDRACULA was exectued? :) :)
  5. S

    How to characterize a mixed signal chip?

    Re: CHIP Charaterixzation Hi Maybe!! you need to check power consumption, leakage current issues Some testing machine have ability to check power & leakage. :)
  6. S

    which is the best backend book

    I think some EDA vendor documents, such as Synopsys, Mentor Graphic, ...etc When they introduce their product, they also tell us some concept about back-end releated issues. Yes, certainly, experience is very important!!! :?
  7. S

    [SOLVED] Which is the best layout tools?

    For manual layout, Virtuoso is good For Auto-place&routing Apollo is not bad :)
  8. S

    What and why is clock synthesis important?

    In RTL level simulation, it's ideal clock meaning zero skew, But after routing, routing path & fan-out loading which cause clock skew. When the clock skew over timing spec. it will cause function wrong!! In many APR tools, they have clock synthesis utility. It's useful!!! :) :o
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    Composer export CDL quesion

    how to cdl in composer Hi, Anybody knows that how to change mos model type name when I use "Export CDL" to generate spice netlist ??? The reference library define pmos model name p1. I need spice netlist with pmos model name PMOS. I tried to modify instance pmos's CDF content in a top cell...
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    Dracula generates .DAT file, is it normal?

    dracula drc inquery smart The PDRACULA version I use is V4.8 That is very strange! I check my command file many times. PDRACULA does not report any errors/warnings message. strange :?: :?: :(
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    Dracula generates .DAT file, is it normal?

    question on dracula I know Dracula generate many *.DAT files in working directory. But I find that it generate a special file, that file name is just -.DAT In my command file, I do not output any file using the name "-". I think it is very stranger!!! :?: How come?
  12. S

    Dracula generates .DAT file, is it normal?

    dracula working directory When I use Dracula to check DRC error, Dracula generated "-.DAT" file in my working directory. Does anyone know that what command in command file create it? Is it normal?????? :?:
  13. S

    Help me about Avant! Apollo

    Hello everybody, In Apollo, we would have main library and reference library(standard cell library for example).Both of them have technology file,separately. What will happen if main library and reference library have different technology file???
  14. S

    About Cadence SKILL program

    skill cadence program hi guys, I want to create pull-down menu in CIW,but I got some troubles. Anyone can help me?? I use hiCreatePulldownMenu to create new menu(A) , and I use hiInsertBannerMenu to insert it, I load this SKILL program(A.il) in ~/.cdsinit After I execute icfb , I can not find...
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    Who can tell me how to design memory?

    It's not easy topics In my opinions, you should read some documents and books, first.

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