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As mentioned in title, which is a typical analog layout flow used in IC design house？We have a too simple flow like schematic>layout>pv>pex>release:-(
Anyone can tell me a detailed flow？THANKS
In my expirence using tsmc 65nm rf process, DEEP NWELL is used to form a separate psub which isolated from substrate. NWELL should overlap DNW outside, in which ntap is added to connect VDD，in other words, nwell is a donut ring covering dnw.
Have time, i can draw a figure.
You didnt used dnw correctly！DNW commonly are used to isolate a clean psub from the whole substrate and it is not for pmos! NMOS are surrounded with ptap connected to VSS， ntap connected to VDD
surround ptap! Of coure, you must overlap nwell above DNW.
PMOS' bulk should be connected to VDD or...
Inductor do have huge areas! In PLL or PA, inductor occupied most of areas. Bur i am not sure if pmoscap is acceptable in performance, i know MIM caps are commonly used in RF design.
You should study some basic on semiconductor! Basiclly, MOS have 4 terminal include Sourece, drain, gate and bulk. As u mentioned bulk is ptap connected to psub and ntap connecnted to Nwell.
Other problerms are about DRC, you should learnt design rule firstly, and cleaned all errors.
Actully, the results depend on your rules, in which you can find which layer is used.
BTW, before you do your drc/lvs, please read the rules firstly, sometimes you can find something important in which.
Good luck!
cadence installation guide redhat 4
This should be called paper:)
I installed IC5141 in openSUSE 10.2 enviroment, but when i invoked icfb, glibc error happen. I will updae IC5141 and try it again.
BTW, thanks the good report!
You should study the process flow first! For TSMC 0.18 process, pwell is not a real well, which is just a "Not Nwell" logic operation and has no special PWELL mask in general process. But in 0.18 rf process, you can achieve Pwell by using deep-nwell, which is isolate with the psub.
Which verification tool did you use? If you used calibre, it can reduce the short devices such as dummy devices, which is must be connected to vdd or gnd. If you use Assura, it will leave the dummy devices, even if they are all short together.
FYI.
Basiclly, there is no difference. The most important thing is to discuss with the circuit designer. You can get to know which pair of transistor need match and what metal layout has specail requirement. And you must tell him which is can not be achieved.
Comunication between you and designer is...
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