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Re: how to write a rising-edge D flip flop program using a Verilog
I found it - I had accidentally added something from a comment block in as code and that is what the issue was. I removed it and then it complied successfully.
always block
here is what I have but it keeps failing:
module DFF(clock,D,Q,Qbar);
input clock, D;
output reg Q;
always block
output Qbar;
assign Qbar = ~ Q;
always @(posedge clock)
Q = D;
endmodule
Any ideas?
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