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Recent content by SLIman

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    How do I asynchronously launch a clock pulse for four counts, then stop

    The LVDS signal is not data, only timed pulses for a camera high power light source (IR). The noise is probably due to a number of factors on a different board (not mine that interfaces with it). Nevertheless, I must clean it up as best as I can. The design works pretty good even with the...
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    How do I asynchronously launch a clock pulse for four counts, then stop

    No, this is a noisy LVDS transmission line. There is an external LVDS to TTL converter that does a pretty decent job of passing "everything" through. I don't have control over this board as it is in production. I have added a schmitt trigger to the input side of my CPLD which cleans things up...
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    How do I asynchronously launch a clock pulse for four counts, then stop

    I'm trying to build a digital filter. I want to kick off an output pulse that runs for just four cycles that is 1.5ms high, 1.36ms low 4 times, then stops and waits for the another valid trigger input to start it all over again. However, After the initial "good" rising edge there is about...
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    FPGA based Robot "Logitraxx" now on Kickstarter

    Hi guys, I recently launched my Robot kit Logitraxx on Kickstarter. Its basically Tamiya type tracked vehicle equipped with Spartan 6 FPGA, onboard USB to JTAG, and plenty of I/O and sensors. If you are looking to learn basic VHDL for FPGAs aimed exclusively at robotics, this is the perfect...

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