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Recent content by sleary

  1. S

    How to write a function in Verilog which takes a vector as input and outputs a vector

    Very simple... function [7:0] convert_nibble_to_char; input [3:0] data; begin convert_nibble_to_char = (data < 4'd10) ? 8'h30 + data : 8'h3f + data[2:0]; end endfunction // convert_nibble_to_char
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