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18f6720 eagle
Important bug was detected in your scheme.
Pin AVDD should be connected to VDD. In other case the initial loading of firmware into PIC18 is failed.
oscilloscope schematics
>>That is not true, normally the input impedance of oscilloscopes is 1 MΩ || ~10-100 pF.
I don’t understand what are you talking about.
The question was why the oscilloscope has limitation +-5V for input voltage.
Do you mean that you know the oscilloscope with such...
build dso oscilloscope
Usually, the input chain of oscilloscopes has low resistance (50..150 Ohm) in accordance with low impedance of cable
which is connected to oscilloscope. The dissipated power for input chain is limited.
oscilloscope frontend
Hi,
>>Skov, just some questions for you:
>>Why EPM3064-7 wasn't fast enough?
Did you write firmware for this project and check it in simulator?
Why do you think that EPM3064-7 is enough?
I think it depends on tasks for CPLD.
My project was fully completed and...
gameboy oscilloscope
2monnoliv:
Hi,
my oppinion:
1) It is recommended to add pull-up resistors for JTAG.
2) CP2101 is more simple than FTDI
3) The trigger scheme should be implemented in CPLD
I made DSO with almost the same architecture.
EPM3064-7 was not fast enough. I was forced to use...
byteblaster mv pull up
I had the problem with BB and EPM7...
The problem was solved by setting the capacitor 100pF between TDI and GND.
Sorry, don't remember exactly - may be it was TDO.
acex 1k10
I'd like to configurate EP1k10 using SP mode and LPT.
I have the following questions.
1) What is the simplest scheme for that? I think two signals should
be enaugh - Data0 and DCLK. I'm ready to wait 1 second after
power ON for reseting of PLD. I don't need nStatus and nConfig...
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