Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi all,
I am very new to the world of CPLD/FPGA and VHDL. For my project, I want to generate 4 clock frequencies (20 MHz 2 nos and 40 MHz 2 nos) from a reference tcxo of 80 MHz. All the four output channels need to be phase matched with each other and with reference tcxo. Also the output...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
