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Recent content by sivasankar

  1. S

    DFT tool fastscan help

    Hi, We are using mentor dft tool "fastscan" for out atpg testing. Here we want to generate WGL file for ATE, We could geneate WGL file for tester, however the port signals order are specified in the netlist is not maintained in WGL. In netlist we have input signals and output signals are mixed...
  2. S

    Maintaining the port in the netlist in Fastscan

    Hi, We are using mentor dft tool "fastscan" for out atpg testing. Here we want to generate WGL file for ATE, We could geneate WGL file for tester, however the port signals order are specified in the netlist is not maintained in WGL. In netlist we have input signals and output signals are...
  3. S

    Negative timing check annotation problem

    negative timing check Hi, I am working Netlist simulation on .13um TSMC library. While loading the design modelsim say that "negative check specify delay to zero" How will I inform the tool to annotate negative delays. I am not using +no_ngchk option. So unless otherwise we specify, it should...
  4. S

    Need "HyperTransport System Architecture" book?

    Hi, Where Can I get this Mindshare "HyperTransport System Architecture" book?. Free download able. Thanks siva
  5. S

    writing synthesizable RTL for async set,async clear flipflop

    Re: writing synthesizable RTL for async set,async clear flip How do we deal with such a design requirement? Siva
  6. S

    writing synthesizable RTL for async set,async clear flipflop

    Hi, I am designing ripple counter to generate a slow clock for low power design, I would like to know how do I design verilog RTL for loading pre determined value to all FF's, so that MSB bit go as a clock. right now I am writing RTL something like this always @(posedge clk or negedge reset_n...
  7. S

    verilog dynamic instantiation ??

    Hi, Does any body know How to replicate a module instantiation for multiple time dynamically in VERILOG? example `ifdef PHY_MEM_4 `define MEM 4 `elsif PHY_MEM_5 `define MEM 5 `endif RAM U_RAM ( cs_n, cas_n ras_n...
  8. S

    waveform editing tool??.

    Hi, The link you had sent to me was about waveform viewer, what I want is waveform drawing tool, where we can draw clock, signals, bus signal....etc it saves lot of time if you use tool. please let me know if you come across any tool which is available for free. siva
  9. S

    waveform editing tool??.

    free waveform drawing tool Hi, Anybody know free waveform editing tool?. so that I can draw the clk,bus,signals very quickly. regards sivasankar
  10. S

    does any one know where I can get DLL model for simulation

    Re: does any one know where I can get DLL model for simulat Hi, I don't have xilinx, I have VCS simulator, required DLL simulatable verilog model. siva
  11. S

    does any one know where I can get DLL model for simulation

    Hi, I am looking for digital delay lock loop(DLL) for verilog simulation, does any one know where I can get it?. regards siva
  12. S

    acrobat reader 5.08 not working in redhat9.0

    Hi, Thankyou, It is working, but why ctrl-p,ctrl-s are not working?. regards siva
  13. S

    acrobat reader 5.08 not working in redhat9.0

    Hi, How do I unset LANG Variable?, I am using bashrc. I have downloaded the linux version of acrobat. reply me siva
  14. S

    acrobat reader 5.08 not working in redhat9.0

    Hi, I have installed acrobat read 5.08 in Redhat linux 9.0, when I read PDF file using "acroread sclrn.pdf" I got this message Warning: charset "UTF-8" not supported, using "ISO8859-1". Aborted so can any one help me what to do?. regards siva
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