Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
some problems with VHDL.I have checked it for many times,but Quartus always report the mistakes.i would appreciate it if you can help me.
the code as follows:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity score is
port(load:in std_logic...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
